The present invention relates generally to slew rate and settling time improvement circuitry and methods for three-stage amplifiers, including chopper-stabilized three-stage amplifiers with notch filtering, chopper-stabilized three-stage amplifiers without notch filtering, and traditional three-stage amplifiers without chopper stabilization and notch filtering.
The closest prior art is believed to include the assignee's U.S. Pat. No. 7,292,095 Entitled “Notch Filter for Ripple Reduction in Chopper Stabilized Amplifiers” issued Nov. 6, 2007 to Rodney T. Burt and Joy Y. Zhang, and incorporated herein by reference. The closest prior art is believed to also include the article “A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter with Synchronous Integration Inside the Continuous-Time Signal Path” by Rod Burt and present inventor Joy Zhang, IEEE Journal of Solid-State Circuits, volume 41, Number 12, December 2006, pages 2729-2736.
FIG. 1 shows a “traditional” basic three-stage amplifier 1A with multipath nested Miller compensation. This circuit configuration can be thought of as including a three-stage high gain signal path including three sequentially coupled stages 2, 3 and 4 having transconductances of gm1, gm2, and gm3, respectively, coupled in parallel with a wider bandwidth two stage signal path including two sequentially coupled stages 5 and 4 having transconductances of gm4 and gm3, respectively. The amount of DC precision of the operational amplifier shown in FIG. 1 is determined by the input stage 2 in the three-stage high gain signal path, while the high frequency response and phase margin are dominated by the two-stage signal path. Proper selection of the transconductances and the compensation capacitances results in the operational amplifier having the bandwidth and settling characteristics of a two-stage Miller compensated operational amplifier with a minimal increase in quiescent supply current Iq being required to achieve a good GBW/Iq (i.e., gain-bandwidth/Iq) ratio.
FIG. 2 shows the operational amplifier configuration of FIG. 1 further including basic chopper stabilization circuitry added before and after the input stage 2 in the high gain three-stage DC signal path. The chopper stabilization has the advantage of substantially reducing offset voltage, offset voltage drift with respect to temperature, and flicker noise, but has the disadvantage of shifting the offset voltage of the input stage 2 to the chopping frequency fs and thereby producing a ripple voltage component in the amplifier output Vout. The chopper-stabilized 3-stage amplifier of FIG. 2 provides excellent DC accuracy and low drift because any low frequency errors are essentially eliminated by the chopping switch. However, the drawback of a chopper-stabilized amplifier is that its output signal includes a ripple component due to the chopping switches. To overcome the output ripple, a switched capacitor notch filter is added after the chopping switch to filter out the ripple, as shown in FIG. 3.
FIG. 3 is a detailed schematic diagram of a three-stage chopper-stabilized amplifier including notch filtering for ripple reduction as described in the assignee's above-mentioned U.S. Pat. No. 7,292,095. In FIG. 3, chopper-stabilized amplifier 1C includes operational transconductance amplifier 2 having an input chopper 9 and an output chopper 10. Choppers 9 and 10 operate in response to clock signals Phase 1 and Phase 2, as shown. Switched capacitor notch filter 15 filters the chopped output of operational transconductance amplifier 2 synchronously with the chopping frequency of output chopper 10 to filter ripple voltage component of operational transconductance amplifier 2. Operational transconductance amplifier 3 amplifies the output of notch filter 15, which operates in response to clock signals Phase 3 and Phase 4. Vin, after being amplified by operational transconductance amplifier 2 and chopped by choppers 9 and 10, and is fed forward into the input of the second operational transconductance amplifier 3, the output of which is applied to the input of operational transconductance amplifier 4.
Notch filter 15 operates to average out the error at the output of the input transimpedance stage 2 during each ½ chopping clock cycle, then transfers the averaged signal to the next transimpedance stage 3. Although notch filter 15 works fairly well with the chopping technique (it reduces the output ripple to a level that is not even visible on an oscilloscope), its averaging function increases the settling time during a large signal slewing operation because notch filter 15 treats the fast changing, large-magnitude Vin signal as an error signal and averages it, as subsequently explained in detail with reference to FIG. 4. The result of the averaging process is that it takes several clock cycles for Vout to reach its final ideal value after a large-signal stewing. Therefore, the settling time of Vout is limited by the number of clock cycles needed to average the error signal to within a specified tolerance. (Even though the chopping clock frequency can be increased to reduce the settling time, a very high chopping frequency will cause many other problems due to parasitic capacitance in the circuitry and will increase the difficulty of implementing the amplifier of FIG. 3.)
There is an unmet need for a three-stage amplifier having fast output stewing rate and fast output settling time.
There also is an unmet need for a three-stage chopper-stabilized amplifier having fast output stewing rate and fast output settling time.
There also is an unmet need for a three-stage chopper-stabilized, notch-filtered amplifier having fast output stewing rate and fast output settling time.
There also is an unmet need for a chopper-stabilized amplifier having extremely low output ripple noise and also having fast output slewing rate and fast output settling time.
There also is an unmet need for a chopper-stabilized operational amplifier having extremely low output ripple noise, very low offset voltage, fast output slewing rate, and fast output settling time.